About the role
Exp- 5 to 10yrs
Location- HYD
- Strong understanding of Analog, Digital, and Mixed-Signal verification methodologies.
- Hands-on experience with:
- Cadence Virtuoso
- Spectre
- AMS Designer
- HSPICE
- Synopsys VCS/Xcelium
- Proficiency in SPICE simulations and circuit analysis
- Strong knowledge of CMOS fundamentals and electronic circuit concepts
- Experience with Verilog, Verilog-A, Verilog-AMS, SystemVerilog, and UVM methodologies
- Understanding of timing closure, STA, signal integrity, and noise analysis
- Scripting experience in Python, Perl, Tcl, or Shell preferred.