About the role
l Should have a very good understanding of semiconductor and analog basics. l
Good hands-on experience in toplevel integration and block level analog layouts like ADC/DAC/PLL/high speed Serdes, Power Management blocks
l Hands-on experience in 7nm, 5nm.
N3E or lower node experience is a plus. l
Good Experience with floor planning, matching, EM/IR and DFM issues and other analog layout related concepts and hands on implementation from scratch.
l Experience of LVS, Density, lower node DRC’s, Parasitic reduction and other lower node challenges.
l Good experience in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc.
l Good problem solving and logical reasoning skills. Good communication skills required.
l Avoid resumes only with Intel project exposure.
TSMC/Samsung/serdes projects are preferable to have in resumes. Analog Mixed signal verification experience.
Understanding CMOS analog design like References, Amplifiers, Comparators, etc..
Running spice and cosim simulations for analog/AMS blocks like ADCs, PLLs etc..
Writing analog checker and running regression across operating conditions.
Digital verification skill and strong knowledge on systemverilog and UVM