About the role
- Develop tests, checkers and coverage to help verify designs.
- Develop understanding of the architecture and microarchitecture of designs.
- SystemVerilog/UVM/C code to generate test content.
- Develop scripts to automate various processes.
- Debug test failures, work with design, verification and modeling teams to fix and verify the fixes.
- Help improve verification processes and contribute to methodology.
- Currently has, or is in the process of obtaining, a Bachelor's degree in Electrical Engineering, Computer Engineering or related engineering fields
- Knowledge of Computer Architecture and Logic Design fundamentals
- Experience thinking critically and creatively on how to verify designs, solve problems
- Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment
- Intent to return to degree-program after the completion of the internship
- Currently has, or is in the process of obtaining, a Masters or PhD degree in Electrical Engineering, Computer Engineering or related engineering fields
- Knowledge of SystemVerilog/VHDL/Verilog/UVM
- Scripting with Python or perl