Design Verification

About the Unit

TCS IAE is redefining the future of industry by embedding intelligence across engineering, manufacturing, asset, and service value chains. Powered by AI, connected ecosystems, and autonomous operations, it transforms insights into action—creating self-optimizing, resilient, and intelligent enterprises at scale. By seamlessly converging the physical and digital worlds, TCS IAE is enabling a new era of AI-first enterprises where systems continuously learn, adapt, and evolve—driving measurable outcomes and shaping how industries operate for the future.

Role: Design Verification (DV)

Roles & Responsibilities

·Develop and execute verification plans aligned with design specifications

·Design and implement UVM-based verification environments and testbenches

·Create and run directed and constrained-random test cases

·Analyze simulation results, debug failures, and report root causes

·Collect and close functional, code, and assertion coverage

·Collaborate with cross-functional teams to achieve first-pass silicon success

Tools and Skills

·Languages & Methodologies: SystemVerilog, UVM, SVA

·Simulators & Debug: VCS, Xcelium, Questa, Verdi

·Coverage: Functional, Code, Assertion Coverage

·Protocols: AMBA (AXI/AHB/APB), PCIe, USB, DDR, SPI, I2C, UART

·Power-Aware Verification: UPF-based simulation

·Scripting: Python / Perl / Shell (preferred)