About the role
Role
Overview
Ananant
Systems is developing an AI-native DSP SoC for 5G/6G wireless, Edge AI, vision,
video, and radar compute. This role focuses on block-level functional
verification of DSP datapath IP—including arithmetic units, SIMD/vector
engines, transform blocks, and convolution engines. The engineer will define
verification plans, develop UVM environments, drive coverage closure, and
ensure verification sign-off in close collaboration with DSP designers.
Key
Responsibilities
Create
block-level verification plans: define objectives, coverage models, risks, and
sign-off criteria.
Develop
UVM testbenches with reusable agents (AXI4-Stream, AHB/APB, custom FIFOs).
Build
algorithmic reference models (C++/Python) for DSP blocks like FFT, LDPC, DCT,
convolution, and MAC arrays.
Implement
self-checking scoreboards with bit-accurate or SNR-based validation.
Drive
coverage-driven verification: analyse gaps, generate targeted sequences, and
manage regressions.
Write
SystemVerilog Assertions (SVA) and conduct formal verification (JasperGold / VC
Formal).
Execute
low-power verification (UPF), X-propagation analysis, and power-domain
behaviour validation.
Deliver
block-level sign-off reports, bug tracking, coverage metrics, and reusable
testbench components for SoC integration.
Requirements
Required
Skills
DomainKey SkillsLevel
UVM
/ SystemVerilogTestbench architecture,
constraints, covergroups, assertionsExpert
Reference
ModellingC++/Python bit-accurate &
SNR-based modelsExpert
DSP
AlgorithmsFFT, LDPC, Turbo,
DCT, convolution, MAC, SADAdvanced
Formal
VerificationSVA, property proofs,
X-propagationAdvanced
Coverage
AnalysisFunctional & code
coverage, closure, exclusionsExpert
Low-Power
(UPF)Isolation/retention, power
sequencingWorking
Scripting
& ToolsPython/Perl/Make,
VCS/Xcelium/Questa, Verdi/DVE, JiraAdvanced
Preferred
Experience
Verification
of DSP datapath IP in wireless (FFT, LDPC, Turbo, Polar), AI inference, video
codec, or radar processing.
Development
of algorithmic reference models with accuracy metrics (SNR, BER, EVM, PSNR).
Hands-on
formal sign-off for datapath control FSMs.
Background
in compute domains like 4G/5G PHY, vision, or radar.
Benefits
Why
Join Us
Work
on a novel unified DSP architecture spanning wireless, AI, video, and radar.
Collaborate
closely with design and architecture teams.
Competitive
compensation and ESOP participation.
Opportunity
to publish methodology innovations (DAC / DATE / DVCon).