About the role
DESIGN VERIFICATION ENGINEER
BENGALURU, INDIA
About the role:
We are seeking a seasoned Design Verification Engineer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions
Responsibilities:
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Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems
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Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards
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Collaborate with software teams to define and implement configurable test benches
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Work with design teams test plans, failure debug, coverage, etc.
Qualifications and Preferred Skills
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BS, MS in Electrical Engineering, Computer Engineering or Computer Science
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8+ years and current hands-on experience in block-level/IP-level/SoC-level verification
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Proficiency in Verilog, SystemVerilog
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Familiarity with industry-standard EDA tools for simulation and debug
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Deep experience with UVM-based test benches
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Experience with modern programming languages like Python
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Knowledge of Arm AMBA protocols such as AXI, APB, and AHB
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Understanding of Arm CHI protocol is a plus
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Experience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NoCs
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Experience with formal verification techniques, emulation platforms is a plus
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Excellent problem-solving skills and attention to detail
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Strong communication and collaboration skills