About the role
Lead Logic Design Engineer
Experience
6-10 years
Job Summary
We are seeking a Lead Logic Design Engineer with deep expertise in micro-architecture and RTL design to lead the development of complex IPs/subsystems. The candidate will provide technical ownership across architecture, microarchitecture, RTL implementation, integration, and silicon bring-up.
Key Responsibilities
- Lead RTL/microarchitecture development for complex connectivity IP/subsystems.
- Translate specifications and system requirements into robust hardware architecture.
- Design high-performance and scalable logic for controllers/subsystems.
- Work across connectivity IP / subsystem layers including Transaction, Data Link, and Physical interface integration as applicable to the role.
- Develop and review RTL using SystemVerilog/Verilog.
- Develop robust mechanisms for flow control, ordering, buffering, arbitration, error handling, and reliability.
- Drive performance, latency, area, and power optimization.
- Collaborate with verification teams to develop verification strategies and debug complex failures.
- Work with SoC integration and physical design teams to ensure successful implementation.
- Lead technical reviews and mentor senior engineers.
- Support post-silicon debug and root-cause analysis.
Required Skills
- Extensive experience in complex connectivity IPs such as PCIE, UALink, Ethernet, CXL, UCIe.
- Strong RTL design experience using SystemVerilog/Verilog.
- Deep knowledge of PCIe architecture and protocol.
- Strong understanding of high-speed data paths, FIFOs, arbitration, flow control, and error handling.
- Experience with simulation, lint, CDC, synthesis, and timing considerations.
- Strong debugging and problem-solving skills.
Preferred
- Experience of working in switching silicon.
- Experience of working on entire cycle from concept to silicon production.