Lead PSV Engineer - Memory subsystem - REQ_2933

Areas of Responsibility:

·Lead and execute Memory Subsystem and LPDDR validation activities across post-silicon environments.

·Develop validation strategies, test plans, test cases and coverage plans for memory controllers, PHY and LPDDR interfaces.

·Perform LPDDR4/LPDDR4X/LPDDR5/LPDDR5X interface validation, including initialization, training, timing and functional testing.

·Validate different memory configurations, frequencies, data rates, channels, ranks and memory densities.

·Debug memory-related failures at SoC, controller, PHY, firmware and board level.

·Work closely with hardware design teams to understand memory controller, PHY, clocking, reset, power and interface architecture.

·Review hardware design specifications, block diagrams, schematics and relevant design documentation.

Experience:

8 to 12 years of experience

·Strong experience in Memory Subsystem validation and debug.

·Hands-on experience with LPDDR4/LPDDR4X/LPDDR5/LPDDR5X

·Good understanding of Memory Controller architecture, DDR/LPDDR PHY, Read/write leveling,Memory channels, ranks and banks, ECC and memory error handling.

·Strong knowledge of post-silicon validation and silicon bring-up.

·Experience in debugging failures across hardware, firmware and software layers.

·Ability to read and understand schematics, block diagrams and hardware specifications

·Good understanding of system-level interfaces such as PCIe, USB, I2C, SPI, UART, JTAG, etc., is an added advantage.

·Understanding SoC and memory subsystem architecture.

·Understanding memory controller and PHY integration

Reading and analyzing schematics and board layouts.