About the role
Job Description
In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on Physical Design Methodologies and sub-micron technology of 16nm and lower technology nodes.
• Must have hands-on experience on PnR Suite from Cadence & Synopsys (Innovus & ICC2)
• Experience in Static Timing Analysis (PrimeTime - SI), EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification (Calibre).
• Understanding the practical application of methodologies and Physical Design Tools, Flow Automation, and Improvements.
• Experience in SOC integration, Low Power and High-Speed Design and Advanced Physical Verification Techniques.
•Excellent Customer interaction, Communication, Teamwork skills and managing a team of 10+
• Should have experience in handling >5M instance count , 1.5GHz frequency designs.
• Should have experience on programming in Tcl/Tk/Perl to automate design process and improve efficiency.
Mandatory Skills
Hands on Work,Design Processes,Physical Design,Physical Verification,Timing Closure
Desirable Skills
Hands on Work,Design Processes,Physical Design,Physical Verification,Timing Closure