About the role
Key Responsibilities
• Work closely with the architects and RTL team on synthesis, LEC and constraints of NXP digital IPs
• Carry out floorplanning, and physically aware synthesis on high performance IPs
• Do timing and power analysis on the db, improve the recipe and provide timing feedback to RTL team
• The Leads or solo owners are expected to work with minimal micro-management needs. He / She should be able to communicate with other project members to manage the task divisions and deliveries. He / She will also be responsible to deliver the weekly Status with desired metrics information.
Key Technical Skills
• Self-starter with 3-12 years of relevant experience in synthesis, LEC and constraints at an IP level. Candidate should be able to set up the synthesis, and LEC flows from scratch.
• Strong fundamentals of synthesis and P&R
• Good scripting knowledge (tcl, perl, python)
• Knowledge of Fusion compiler, Genus/Innovus and Primetime"