Senior Analog Layout Engineer

Senior Analog Layout Engineer

🧩 Technology Node: TSMC 40nm

🎯 Domain: AMS (Analog Mixed Signal) Layout

Role Summary

We are looking for a highly skilled Senior Analog Layout Engineer with strong hands-on experience in TSMC 40nm node and AMS layout design. The ideal candidate should be capable of independently handling floorplanning, layout execution, verification, and sign-off activities while ensuring strict adherence to design and foundry guidelines.

Key Responsibilities

• Perform block-level and sub-block level layout implementation based on design documents.
• Create and optimize floorplans ensuring optimal matching, parasitic control, shielding, and noise isolation.
• Ensure 1-to-1 matching between layout devices and simulation hierarchy.
• Translate sub-block schematics into layout maintaining hierarchical consistency.
• Perform DRC checks and resolve violations until error-free.
• Perform LVS checks and resolve mismatches until clean.
• Ensure compliance with TSMC 40nm foundry layout rules.
• Provide extracted netlists for back-annotation to Design Engineering (DE).
• Incorporate review remarks, customer feedback, and back-annotation updates.
• Follow all general layout guidelines and document compliance.
• Add relevant layout observations and enhancements to the Block Review Document.
• Take corrective actions to ensure layout meets:
• Design document requirements
• Customer remarks
• Back-annotation constraints

Required Technical Skills

• Strong experience in TSMC 40nm node
• Deep understanding of AMS layout methodologies
• Expertise in:
• Matching techniques (common centroid, interdigitation)
• Guard rings & shielding
• High-voltage spacing rules (if applicable)
• Noise isolation strategies
• Parasitic-aware layout
• Strong experience in:
• DRC / LVS closure
• Extraction and back-annotation flows
• Experience with hierarchical layout build-up
• Ability to independently own layout from floorplan to sign-off

Experience Required

✔ 5–8 Years of relevant experience in Analog/Mixed Signal Layout

✔ Proven tape-out experience in advanced nodes (40nm preferred)