About the role
Locations: Hyderabad / Bangalore
Experience: 4 to 12 Years
Job Type: Full-time
Open Positions:
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Hyderabad: 3 Positions
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Bangalore/Hyderabad: 5 Positions
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Hands-on involvement in full-chip DFT design, implementation, and vector generation.
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Experience with JTAG, Boundary Scan, and related simulation & verification processes.
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Develop and execute DFT insertion, scan compression, ATPG generation, and validation.
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Strong experience in Scan, Compression, ATPG, and DFT simulations.
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Proficiency with industry tools from Mentor Graphics, Synopsys, or Cadence.
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Deep understanding of DFT architecture, patterns, and fault models.
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Experience in debugging and validating scan insertion and ATPG coverage.
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Good understanding of SoC architecture and hierarchical DFT implementation.
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Prior experience working with cross-functional teams including RTL and Physical Design.