About the role
Perform channel modeling, extraction, and eye analysis for high-speed interfaces.
Conduct pre-layout and post-layout SI simulations to ensure compliance with interface standards.
Analyze crosstalk, reflections, jitter, insertion loss, return loss and TDR.
Model, analyze and provide recommendations on board PDN.
Perform AC/DC droop analysis, target impedance profiling to ensure clean power delivery to high-current ASICs, SoCs, and FPGAs.
Collaborate with Hardware and ECAD teams to optimize signal integrity and power integrity performance.
Provide design guidelines balancing both SI and PI constraints.
Generate technical reports and provide design recommendations based on simulation results.
Strong understanding of signal integrity and power integrity concepts for high-speed serial and memory interfaces.
Hands-on experience with:
Ansys HFSS
Altium Designer
Ansys Siwave
Siemens hyperlynx 2D & 3D
Familiarity with JEDEC, LPDDR4/LPDDR5, PCIe 4/5, GMSL, FPD -Link, MIPI-CSI, USB, Ethernet and other automotive standards.
Ability to perform board level timing analysis using tools.
Strong analytical and problem-solving skills with good communication and documentation skills.
Preferred Skills
Ability to use ECAD tools.
Basic knowledge on EM/Compliance based simulation and analysis