SOC Design Verification Engineer

UST Title – Technical Lead I - VLSI

Who we are:

At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 30+ countries, we build for boundless impact—touching billions of lives in the process. Visit us at .

Role Overview

UST is looking for experienced Senior/Lead Design Verification Engineers with strong expertise in IP, Subsystem (SS), and SoC-level verification. Candidates should have deep knowledge of SystemVerilog, UVM, verification methodologies, and design architecture, with the ability to drive complex verification activities, guide team members, and ensure high-quality delivery.

Key Responsibilities

• Own end-to-end verification activities for complex IPs, subsystems, and SoCs, from specification analysis through verification sign-off.

• Design and develop scalable, reusable SystemVerilog/UVM-based testbench environments.

• Define verification strategies, develop test plans, and drive functional coverage and verification closure.

• Understand design architecture, microarchitecture, IP integration, internal data flows, and inter-block interactions.

• Debug complex design issues, perform root-cause analysis, and collaborate with design and architecture teams.

• Develop assertions, scoreboards, reference models, reusable VIPs, and automation scripts.

• Lead technical reviews, mentor engineers, and drive verification best practices and quality improvements.

• Drive task planning, effort estimation, risk identification, execution tracking, and timely delivery of milestones.

Required Skills

• 5–15 years of hands-on experience in IP, subsystem, and/or SoC Design Verification.

• Strong expertise in SystemVerilog, UVM, constrained-random verification, SVA, and functional coverage.

• Proficiency in C programming and scripting languages such as Python, Perl, or Shell.

• Strong understanding of AMBA protocols, including AXI, AHB, and APB.

• Experience in testbench architecture, reusable verification components, regression debug, and coverage closure.

• Good understanding of SoC architecture, microarchitecture, IP integration, and subsystem interactions.

• Hands-on experience with industry-standard simulation, debug, and coverage tools.

Preferred Skills

• CPU, GPU-based verification and processor architecture knowledge, including pipelines, caches, and memory subsystems.

• PCIe and Ethernet protocol knowledge or hands-on verification experience.

• Experience in subsystem integration, performance verification, and protocol compliance.

• Experience in reusable VIP development, verification automation, and productivity improvements.

Expected Competencies

• Strong technical ownership and independent problem-solving capability.

• Ability to lead complex verification activities from planning through sign-off.

• Effective planning, execution, risk management, and delivery tracking.

• Ability to mentor engineers, review technical deliverables, and improve team productivity.

• Strong communication and collaboration skills when working with design, architecture, and customer teams.

Location and Long-Term Opportunity

This role is based at UST Ahmedabad, Gujarat, with opportunities to contribute to complex IP, subsystem, and SoC verification programs while strengthening the local engineering team.

We are looking for candidates seeking a long-term career with UST, with a strong focus on technical leadership, engineering excellence, continuous improvement, and reliable delivery.

What we believe:

We’re proud to embrace the same values that have shaped UST since the beginning. Since day one, we’ve been building enduring relationships and a culture of integrity. And today, it's those same values that are inspiring us to encourage innovation from everyone, to champion diversity and inclusion and to place people at the centre of everything we do.

Humility:

We will listen, learn, be empathetic and help selflessly in our interactions with everyone.

Humanity:

Through business, we will better the lives of those less fortunate than ourselves.

Integrity:

We honour our commitments and act with responsibility in all our relationships.

Equal Employment Opportunity Statement

UST is an Equal Opportunity Employer. We believe that no one should be discriminated against because of their differences, such as age, disability, ethnicity, gender, gender identity and expression, religion, or sexual orientation.

All employment decisions shall be made without regard to age, race, creed, colour, religion, sex, national origin, ancestry, disability status, veteran status, sexual orientation, gender identity or expression, genetic information, marital status, citizenship status or any other basis as protected by federal, state, or local law.

UST reserves the right to periodically redefine your roles and responsibilities based on the requirements of the organization and/or your performance.

• To support and promote the values of UST.

• Comply with all Company policies and procedures