About the role
Job
Description: SoC Verification Engineer
Company: Ananant Systems
Location: Noida / Bengaluru
Department: Silicon Engineering — Design
Verification
Experience: 6–14 years
Education: B.Tech / M.Tech in
Electronics, Computer Engineering, or Electrical Engineering
About
the Role
Ananant
Systems is developing a proprietary AI-native DSP SoC for 5G/6G wireless, Edge
AI inference, Vision AI, camera, video, and radar applications. We are looking
for an experienced SoC Verification Engineer to own end-to-end functional
verification of the full chip — from IP integration to pre-silicon sign-off and
post-silicon support.
Key
Responsibilities
Develop
and own the SoC-level verification plan, coverage model, and traceability
matrix.
Build
and maintain the UVM-based SoC testbench including top-level environment,
virtual sequencer, chip-level scoreboard, and coverage infrastructure.
Integrate
and verify all major interfaces: PCIe Gen3/4, USB3, JESD204B, MIPI CSI-2/DSI,
DDR/LPDDR, AXI/AHB/APB, and other peripherals.
Develop
and execute end-to-end data path verification for key workloads (5G/6G, AI
Inference, Video/Camera, Radar, Vision AI).
Verify
DMA, Interrupt Controller, Clock/Reset, Power Management (UPF), and DFT (Scan,
MBIST, LBIST, JTAG).
Own
regression management, coverage closure, gate-level simulation with SDF, and
tapeout sign-off.
Requirements
Required
Skills & Competencies
Expert
level: UVM (SoC environment, virtual sequencer, chip scoreboard), SystemVerilog,
regression management & scripting (Python/Perl/Shell).
Advanced
level: Peripheral VIP integration (PCIe, USB3, JESD204B, MIPI, DDR), low-power
verification (UPF), clock/reset, DFT simulation, end-to-end data path checking.
Hands-on
experience with VCS/Xcelium/Questa and waveform debug tools.
Strong
domain understanding of wireless, AI, or multimedia SoCs.
Mandatory
Experience
Named
contributor on at least 2 commercial SoC tapeouts (16nm or below) with
full-chip verification ownership.
Direct
ownership of at least one major verification domain (peripheral IO, power
management, or end-to-end datapath) through tapeout.
Post-silicon
bring-up experience is highly preferred.
Benefits
What
We Offer
Opportunity
to verify a cutting-edge AI-native DSP SoC with diverse workloads.
Direct
collaboration with design and implementation teams.
Competitive
compensation + ESOPs in an early-stage semiconductor startup.
Exposure
to advanced FinFET technology tapeout.