Staff Engineer, ASIC Analog Design

Req. ID:

JR105254 Staff Engineer, ASIC Analog Design

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

### Key Responsibilities

• Be part of a highly skilled and challenging high-speed PHY design team working on advanced technology nodes (12nm and below).
• Own analog sub-blocks within the PHY and drive specification, design, simulation, reliability, and mixed-mode verification.
• Leverage AI-enabled tools to improve productivity and decision-making.
• Drive layout implementation through mask designers while ensuring compliance with process rules and DFM requirements.
• Participate in design reviews with internal teams and customers, explaining design choices and robustness.
• Collaborate with cross-functional teams across multiple global locations.
• Create IP EDA views including Behavioral models, Verilog-A, timing views, and abstracts.
• Participate in silicon bring-up, characterization, and correlation of silicon results with models and simulations.
• Mentor and guide junior engineers.
• Competitive compensation and equal opportunity workplace.

### Required Skills

• Strong analog/mixed-signal CMOS circuit design experience in deep sub-micron technologies (2nm to 28nm).
• Experience in High-Speed Memory Interfaces (DDR3/4/5, LPDDR5/6, GDDR5/6/7) or SerDes Interfaces (PCIe, MIPI, HDMI, USB, SATA, etc.).
• Full ownership experience of at least one critical PHY sub-block such as:
• PLL
• DLL
• CDR
• High-speed Receiver with Equalization
• Transmitter Front-End
• High-Speed Data Path
• Deep understanding of analog and mixed-signal design concepts with high-speed link experience.
• Mandatory experience in SerDes and/or Parallel Interfaces.
• Mandatory experience with TX/RX Equalization techniques (FFE, CTLE, DFE).
• Experience with CDR and clocking architectures.
• Hands-on experience in FinFET technologies (10nm and below).
• Ability to develop block-level specifications based on link budgets.
• Experience in system-level modeling using Verilog-A and/or Python.
• Experience working with Packaging and Board teams.
• Knowledge of ESD design considerations.
• Experience in lab testing and collaborating with validation teams for data analysis.
• Experience designing high-speed I/O cells such as DDR, LVDS, HSTL, and CML.
• Experience with power delivery circuits including Bandgap, LDO, and Bias circuits.
• Strong understanding of AMS design, advanced CMOS, and FinFET technologies.
• Knowledge of mismatch analysis, Monte Carlo simulations, transistor-level noise analysis, and deep sub-micron device physics.
• Experience supervising complex analog layouts and defining IP floorplans.
• Hands-on experience with industry-standard tools such as Cadence ADE, Spectre, AMS Verification, EM/IR flows, MATLAB, and Calibre.
• Working knowledge of mixed-mode simulation, signal integrity, and ESD analysis.

### Education & Experience

• M.S./M.Tech or B.S./B.E. in Electronics.
• Experience Required: 5+ Years.

Job Profile(s):

ASIC Engineer 4

Relocation level: (TBD)

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