About the role
Key skills :-- RTL coding / RTL Design , ASIC / SOC / ASIC Design, Spyglass , System Verilog / Verilog,CDC,
Pls find detailed JD for RTL Design Position: Hyderabad.
Exp Range: 4-9 Yrs
Ctc :- 28 LPA Max
JD:
- Solid knowledge of digital concepts and the ASIC design flow.
- Experience in RTL coding and developing testbenches in Verilog for functional verification. SV is a plus.
- Hands-on experience with RTL integration and hierarchical understanding of any SoC design.
- Should be good with navigating from requirement to design implementation.
- Proficient in debugging at the RTL level, including waveform review and lint warning resolution.
- Handy in shell scripting (TCSH) or TCLSH for design automation.
- Experience in Synthesis flow & understanding of timing concepts is a plus.
- Surface-level understanding of ASIC digital design stages, including effective handshake between different stages.
- Understanding of Memory designs is an added advantage.
- Excellent oral and written communications skills.
- Proactive, creative, curious, and motivated to learn and contribute.
- Strong collaboration skills and ability to work in a team environment.