RTL Design

About the Unit

TCS IAE is redefining the future of industry by embedding intelligence across engineering, manufacturing, asset, and service value chains. Powered by AI, connected ecosystems, and autonomous operations, it transforms insights into action—creating self-optimizing, resilient, and intelligent enterprises at scale. By seamlessly converging the physical and digital worlds, TCS IAE is enabling a new era of AI-first enterprises where systems continuously learn, adapt, and evolve—driving measurable outcomes and shaping how industries operate for the future.

Role: RTL Design Engineer

Roles & Responsibilities

·Develop high-quality RTL using Verilog/SystemVerilog based on specifications and micro-architecture

·Define and implement clock, reset, and interface logic

·Ensure lint, CDC/RDC, and static checks are clean before handoff

·Support synthesis readiness, constraints awareness, and FE-BE coordination

·Implement low-power intent using UPF/CPF

·Integrate IPs and support subsystem/SoC-level integration

·Collaborate with DV, DFT, STA, and PD teams for closure and signoff

·Develop scripts for automation and quality improvement

Tools & Skills

·Languages: Verilog, SystemVerilog

< span style="font-family:Symbol;mso-fareast-font-family:Symbol;mso-bidi-font-family: Symbol">·Checks: Lint, CDC/RDC, LEC

·Synthesis Awareness: Design Compiler, Genus

·Low Power: UPF/CPF

·Protocols: AMBA (AXI/AHB/APB), SPI, I2C, UART (as applicable)

·Scripting: Tcl, Python, Shell